Short answer. An enable pin is a control input, so its asserted level must be read from the exact model document. In the current ERDILRF records, LR1000E2 uses an active-high SW-SHOT function enable, while LRF3000A1 powers on at a low level. The two lines cannot share one assumed GPIO polarity. Their published timing information is also different: LR1000E2 publishes a startup limit but leaves response time on request; LRF3000A1 publishes a response expression that can be turned into a clearly labelled arithmetic budget.
Read the model row before wiring
Both modules list a 3.3–5 V supply range, but that is the module supply input. It does not tell you which voltage the host must drive on the enable pin, nor does it prove a UART signal level. The pin function and active state must come from the model-specific pin table.
| Model | Supply entry | Enable definition | Published timing and power entries |
|---|---|---|---|
| LR1000E2 | 3.3–5 V | Pin 6 SW-SHOT: function enable, active high; the source note says it is compatible with an active-low control requirement. | Startup ≤200 ms; response time on request; sleep power <1 mW; standby power <0.3 W. |
| LRF3000A1 | DC 3.3–5 V | Pin 6 Enable: power on at low level. | Standby ≤1 mW when enable is high / ≤350 mW when enable is low; response ≤160 ms + 100–517 ms (start-up + first ranging). |
The rows are not interchangeable. For LR1000E2, “active high” describes the source-stated function control, while the document does not publish a first-valid-reading response time. For LRF3000A1, the table explicitly ties the power state to the enable level. Do not copy either polarity to a third model.
Why polarity and signal voltage are separate checks
A shared controller often fails in one of two ways: its default GPIO state holds one module on and another module off, or the designer assumes that a 3.3–5 V supply range is also the UART or enable logic specification. Keep those questions separate in the schematic review. LRF3000A1 documents its serial TX and RX pins as TTL 3.3 V. This article makes no equivalent UART-level claim for LR1000E2 from its supply row.
If an interface circuit uses an open-drain stage, Texas Instruments’ open-drain application note explains that an external pull-up or pull-down is needed to hold a defined state, and that the resistor and logic decision depend on the asserted level and the voltage limits of both connected devices. That guidance is about the host interface design; it does not change the active level written in an ERDILRF model document. Confirm the actual input limits before selecting a translator or pull resistor.
Make a wake-up budget without inventing a specification
LRF3000A1 provides a useful example of how to show the arithmetic and its limits. Taking the largest published start-up and first-ranging terms:
published-term arithmetic = 160 ms + 517 ms = 677 ms
This is an upper arithmetic budget from the documented expression, not an ERDILRF bench measurement and not a promise that a host will receive a valid frame by 677 ms. Your acceptance test still has to timestamp power application, the enable transition, the first checksum-valid response and any host-side filtering. The 100 ms lower term is retained in the source expression; using 517 ms here is intentionally conservative for a planning bound.
LR1000E2 cannot be given the same calculation from the current record. Its startup entry is ≤200 ms, but its response-time entry is “On request.” Use the 200 ms value as a startup specification only, then obtain the response requirement for the delivered configuration. A first reading observed earlier or later on a bench does not rewrite the published field.
Bench checklist for an enable-controlled design
- Freeze the identity. Record the exact model, document revision and pin numbering. Do not use a family default.
- Write the safe state. Before applying module power, configure the host GPIO so the line is at the documented non-running state. For LRF3000A1, that means checking the high-enable standby state; for LR1000E2, check the active-high SW-SHOT definition and the source note about an active-low control requirement.
- Observe the line and current. Use a scope or logic analyser together with supply-current capture. Confirm that the measured level changes in the intended direction and that the standby/working current state agrees with the model row.
- Timestamp the complete event. Log power-good, the enable edge, the first valid protocol frame and the host’s accepted reading. Reject frames that fail the documented validation rule.
- Repeat the transition. Exercise the same sequence across the power-cycle and duty-cycle cases required by your product acceptance plan. Record the longest observed interval and keep it separate from the published bound.
- Review the host path. Check reset sequencing, translator direction, pull resistor values and the controller’s boot default. A correct module polarity can still be defeated by a GPIO that floats or changes state during reset.
Keep this check next to the pinout
The existing pinout and wire-colour guide is useful for connector orientation and signal naming. It only gives a brief polarity warning. This article adds the per-model power-state table, the documented-versus-unpublished timing distinction and a repeatable wake-up acceptance sequence. The broader UART integration guide covers frame handling; it should not be used to infer an enable polarity for a different model.
Contact ERDILRF with the model, host voltage domain and required duty-cycle timing when the delivered configuration needs a written enable or first-reading check.